1. Field of the Invention
The present invention relates to an address translation circuit. More particularly, the invention relates to an address translation circuit for switching address spaces through address translation.
2. Description of the Related Art
There are cases where ordinary processors containing a CPU (central processing unit) core each are later furnished with an additional cache memory arrangement for speed enhancement. For these processors, simply preparing programs without being aware of the added cache can lead to various problems. For example, an indifferently prepared program may let its infrequently-used program functions be held in the cache memory. This will result in a reduced cache hit rate of the entire program and hamper the effort for speed enhancement.
Some systems with additionally-equipped cache memory desire that programs having run on the previous hardware with no cache be run on the new hardware with no modifications (i.e., upward compatibility desired). To utilize the added cache effectively entails rewriting the programs. Simply adding a cache memory feature to hardware may thus involve preparing two kinds of programs, programs prepared to maintain upward compatibility, and programs arranged to use the cache memory effectively.
The problems above are resolved typically by dynamically switching the use and nonuse of cache memory for access to certain address areas. Such dynamic switching is carried out illustratively using a TLB (translation look-aside buffer) feature. The TLB is a buffer that permits translation between virtual and physical addresses. Specifically, the input virtual address is compared with the virtual addresses of the entries in the buffer. In the case of a match, the physical address of the matching entry is output (as described illustratively in Japanese Patent No. 2704112, FIGS. 2A and 2B).